This invention relates to the “capture” of a synchronized clock signal in clock synchronization circuitry. More particularly, this invention relates to clock synchronization circuitry that temporarily provides a synchronized clock output signal without a reference clock input signal. This invention also relates to clock synchronization circuitry that provides a synchronized clock output signal with little or no jitter caused by the reference clock input signal.
Clock synchronization circuitry is used to generate a synchronized clock signal based on a reference clock signal. The synchronized clock signal is ideally in phase with the reference clock signal. One type of clock synchronization circuit is a delay-locked loop (DLL). A DLL uses a variable delay circuit to add phase delay to the input reference clock signal before it is output from the DLL. The DLL uses a phase detector to measure the phase difference between the output of the DLL and the reference clock and to adjust the variable delay to minimize the phase difference.
Another type of clock synchronization circuit is a synchronous mirror delay (SMD). The SMD uses a matched pair of delay arrays, a forward delay array and a backward delay array, to output a delayed clock signal synchronized to the input reference clock signal. The reference clock signal is input into the forward delay array. After a set number of clock cycles, a mirror control circuit is triggered to transfer the clock signal from the forward delay array to the same delay stage of the backward delay array. The clock signal spends the same amount of time in the backward delay array as it does in the forward delay array before being output by the SMD. The total delay through both delay arrays synchronizes the output clock signal to the reference clock signal.
Yet another type of clock synchronization circuit is a measure-controlled delay (MCD). In an MCD, the input reference clock signal is provided to two delay arrays, a measure delay array and a forward delay array. After a set number of clock cycles, a measure circuit is triggered to (1) measure the progress of the clock signal propagating through the measure delay array and (2) output the clock signal from the forward delay array at the same delay point as measured in the measure delay array.
In high speed memory devices, these types of clock synchronization circuits may be used to control the precise timing of memory access. Each of these circuits requires an input reference signal in order to generate the synchronized clock signal. During a power-down state, turning off as much circuitry as possible reduces power consumption. However, the reference signal, its associated clock distribution circuitry, and the clock synchronization circuitry are not typically turned off during a power-down state. This is so because many clock cycles are needed to output a valid synchronized clock signal after exiting a power-down state, and high speed memory devices require the presence of synchronized clock signals immediately upon exiting the power-down state.
In view of the forgoing, it would be desirable to be able to provide clock synchronization circuitry that continues to output a synchronized clock signal after the input reference clock signal is removed. Thus, for example, during a power-down state, the reference clock signal distribution circuitry may be powered-down.
The output of synchronization circuitry may also be susceptible to the jitter of the input signal. Jitter is short-term random variations in the timing of a periodic signal. In a clocked system, these random variations in the timing of a clock signal may cause timing errors.
In view of the foregoing, it would be desirable to be able to provide clock synchronization circuitry that reduces input referred jitter in the synchronized clock signal.